IEEE TRANSACTIONS ON CAD OF ICS AND SYSTEMS 1 Processor Array Design withFPGA Area

1 Processor Array Design with FPGA Area Constraint Joseph A. Fernando, Jack S.N. Jean Abstract|Digital signal processing algorithms with multiple shift-invariant dependence graphs (DGs) can be mapped to FPGA hardware in many di erent types of systolic processor arrays. Because of the nite amount of hardware resources, the problem is to use a \right" amount of hardware in a speci c con guration so to maximize the processing speed. In this paper, the problem of nding the right processor array con guration is formulated as a constrained optimization problem where the cost function includes not only the cost of individual processor arrays but also the cost of interfacing circuits. Three heuristic algorithms are presented for the optimization problem. Among them, both the L-th axial neighbor algorithm and the simulated annealing algorithm produce good results on a test case. Simulation results on the test case also indicate that the initial con guration is important in getting a good con guration for both algorithms. The L-th axial neighbor algorithm has the extra advantage of requiring less amount of performance tuning. Keywords|Algorithm Mapping, Computer-Aided Design, Dependence Graph, FPGA, Processor Array, Systolic Array.